An integrated circuit (IC) chip includes a stack of several levels of sequentially formed layers to define devices (e.g., field effect transistors (FETs) and other active and passive components). In a typical complementary insulated gate FET process, layers are formed on a wafer to form the devices on a surface of the wafer. The surface may be a silicon layer on a silicon on insulator (SOI) wafer, as an example.
In finFET devices, for example, a dummy gate can cover an isolation trench between a pair of neighboring finFETs to enable a single diffusion break therein. The devices further comprise an epitaxial source region and drain region formed within the substrate, e.g., fin structures, with spacers formed along the finFETs and dummy gate. However, the patterning of the isolation trench to reach the required small critical dimensions (CD) is difficult with conventional lithography and etch techniques available. Furthermore, during formation of the circuits, the isolation trench can become larger than the dummy gate, and the epitaxy (epi) of the source region and drain region can grow non-ideally, which results in asymmetric growth resulting in facets. This is especially problematic when trying to land source and drain contacts on the epi of the source region and drain region. In this case, the contact area will not be positioned as desired, which may result in current crowding issues. This decreases yield, increases leakage and results in single diffusion break (SDB)/double diffusion break (DDB) device performance mismatch.